Conventional DRAM (dynamic random access memory) structures may generate a DQS (data strobe) signal that is used by a memory controller to maintain synchronization with the DRAM. Since the line carrying the DQS signal may float between transactions, noise and/or false transitions might be encountered when the DRAM is not actively driving. In order to qualify the state of the DQS signal, the memory controller may trigger a receive enable (RcvEn) signal after expiration of a calculated delay from a read command being sent to the DRAM, wherein the receive enable signal is frequently trained to precisely position itself relative to the rising edge of the DQS signal and the memory controller may ignore the DQS signal when the receive enable signal is deasserted.
While a “weak leaker” resistance may be applied to the line carrying the DQS signal in order to eliminate noise encountered when the DRAM is not actively driving, there remains considerable room for improvement. Other embodiments may use a weak leaker or weak resistor pulldown on a DQS_P (e.g., DQS positive signal in differential signaling) and/or a weak resistor pullup on a DQS_N (e.g., DQS negative signal in differential signaling) to keep DQS in the logical low state when the DRAM is not driving. Such a solution, which may be used in addition to or instead of the RcvEn qualification, may potentially provide a more deterministic DQS value that only toggles during actual read operations. In any case, there remains considerable room for improvement.
For example, back-to-back reads (e.g., from multiple ranks in the DRAM) may create significant ringback noise that calls for a relatively low weak leaker resistance value (i.e., a “strong” leaker) in order to sufficiently keep the DQS signal logical low despite the ringback noise. Such a strong leaker may create DQS duty cycle distortion, which may have a negative impact on read timing margins during normal operation (e.g., when the DRAM is actively driving the DQS signal). This impact of both ringback and duty cycle distortion may be even more pronounced in systems having longer trace lengths between the DRAM and the memory controller.